-- Copyright(C) 2005 by Xilinx, Inc. All rights reserved. -- The files included in this design directory contain proprietary, confidential information of -- Xilinx, Inc., are distributed under license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid license agreement with Xilinx, Inc. -- This copyright notice must be retained as part of this text at all times. This zip file contains the design files for the ISE 7 Indepth tutorial . ----------------------------------------------------------------------- Installation instructions -------------------------- Unzip the file into $XILINX\ISEexamples install directory or any directory with READ/Write permissions. Documentation ------------- Refer to the ISE 7 indepth tutorial available at: http://support.xilinx.com/support/techsup/tutorials/index.htm wtut_sc is a top level schematic type project of a Stop Watch. DESIGN TYPE: Foundation ISE CONTROLS Inputs: ------- • CLK - System clock for the Watch design. • STRTSTOP - Starts and stops the stoopwatch. This is an active-low signal which acts like the start/stop button on a runner's stop-watch. • RESET - Resets the stopwatch to 00.0 after it has been stopped. Outputs: -------- • seg_a, seg,b, seg_c, seg_d, seg_e, seg_f, seg_g, seg_dp These outputs drive the individual segments and the decimal point for all four digits of the stopwatch design. The digits of the stopwatch are displayed on 7-segment LED displays. • an(3:0) - This is a one-hot vector signal which drives the anodes of the four 7-segment LED displays to determine which display will be lighted. Functional Blocks ----------------- The completed design consists of the following functional blocks. Most of these blocks do not appear on the schematic sheet in the tutorial project until after you create and add them to the schematic in this tutorial. • CLK_DIV_262k Schematic-based macro which divides a clock frequency by 262,144. • DCM1 Clocking Wizard macro with internal feedback, frequencycontrolled output and dutycycle correction. The fx output converts the 50Mhz clock of the Spartan3 demo board to 26.2144Mhz • DEBOUNCE Schematic module implementing a simplistic debounce circuit for the strtstop input signal. • HEX2LED HDL-based macro. This macro decodes each of the digit values from binary to 7-segment display format. • LED_control Schematicmodule controlling the data multiplexing to the four 7-segment LED displays. • STMACH_V State Machine macro defined and implemented in StateCAD. • TEN_CNT CORE Generator™ 4-bit, binary encoded counter. This macro outputs a 4-bit code that is decoded to represent the tenths and hundreths digits of the stopwatch. • TIME_CNT Schematic-based module which counts from 0:0 to 9:59 decimal. This macro has three 4-bit outputs, which represent the minutes and seconds digits of the decimal value. SIMULATION: Behavioural and RTL Simulation done using VHDL Testbench (stopwatch_tb.vhd). For support information and contacts please see: http://support.xilinx.com or http://support.xilinx.com/support/services/contact_info.htm