SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = c:\temp\case\wtut_sc\wtut_sc_completed\tmp
SET speedgrade = -4
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
# SET outputdirectory = c:\temp\case\wtut_sc\wtut_sc_completed\
SET device = xc3s200
# SET projectname = coregen
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = ft256
SET createndf = False
SET designentry = VHDL
SET devicefamily = Spartan3
SET formalverification = False
SET removerpms = False